The present invention generally relates to a central processor-based controller for an array of non-volatile memory devices. More particularly, this invention relates to the queuing of commands to the memory devices and the polling of the memory devices in an efficient manner to determine when the memory devices have finished processing the previous command and are ready to accept a subsequent command.
Mass storage devices such as Serial Advanced Technology Attachment (SATA) or Small Computer System Interface (SCSI) interfaced drives are rapidly adopting non-volatile memory technology, such as flash memory components or another emerging solid-state memory technology, including phase change memory (PCM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), ferromagnetic random access memory (FRAM), organic memories, or nanotechnology-based storage media such as carbon nanofiber/nanotube-based substrates. Currently the most common solid-state technology uses NAND flash memory components as inexpensive storage memory, often in a form commonly referred to as a solid-state drive (SSD).
NAND flash memory has several advantages over hard disk technology based on spinning magnetic media. Briefly, flash memory devices provide random access read and write capability and access times which are more consistent and much shorter than hard disks, measured in terms of microseconds rather than milliseconds. Even so, a single flash memory device does not have the required bit density in order for an SSD to compete in terms of storage size with a hard disk. Therefore, it becomes desirable for SSDs to incorporate multiple devices in order to increase the available storage size.
Flash memory devices cannot be directly interfaced to a computer processor or storage interface bus and require a separate memory controller device in order to perform certain functions, including functions that are required to compensate for features inherent in SSD technology.
When a single memory controller is required to operate with multiple memory devices, it can do this using a single memory bus which connects to each device in parallel. Individual devices can be separately enabled using an individual chip select signal which allows the devices to operate in parallel without interfering with each other's operation. This means that a command to a device such as erase block (which can take many cycles to execute, but does not require use of the memory bus while executing) can be interleaved with read and program (write) commands to other devices, thereby providing a better throughput of data despite being limited to a single physical bus.
In order to control the access of multiple devices to the same bus, arbitration of access to the bus is required. A state machine can keep track of what commands are outstanding on which devices and can have knowledge of when they will roughly complete and therefore know when the command completion status can be polled and also know when new commands can be issued to other devices in the intervening time while the bus is free. Central to this process is receiving an indication from each device as to when the device is busy internally processing a command, when the device has completed the command (and needs to return status and/or data), and when the device is free to accept another command. For this purpose manufacturers generally provide a physical pin on the memory device to indicate a ready/busy status and/or a read status command which will return the current status.
There is, however, a limit to the number of devices that can use a single bus, as the extra wiring to each new device increases the track lengths from the controller and the increased impedance/capacitance of the wiring subsequently limits the frequency of operation of the bus.
In addition, operating multiple devices in parallel, while providing some improvement, still does not fully solve the problem of lack of storage capacity and providing maximum performance improvement. In order to give even more capacity and performance, devices operating in parallel can be used. With a non-volatile memory storage controller, multiple memory bus lanes or channels are used. Each channel operates independently and in parallel, thereby multiplying the storage capacity and overall input/output performance by the number of channels employed.
This technique can be combined with the attachment of multiple devices in parallel on each channel, where each device is referred to as a bank and an individual device in the array becomes addressable by its channel number and bank number. For example, with eight channels and eight banks on each channel, for a total of sixty-four devices, checking the status can become an onerous task for the controller. In particular, a system which checks the status of each memory bank on a regular basis irrespective of whether commands are being processed on it or whether any commands are queued waiting to be sent to it, will be operating inefficiently as in many cases the status is not required at that time.
What is therefore desired is a method of polling the status of memory banks at a certain time only if the system can make use of that poll status, thereby reducing the time spent polling so as to make the system more efficient.